- CPU
- 8-bit turbo 80C52 architecture - 4 cycles/ 1machine cycle - instruction level compatible with Intel 80C52
- 15KB FLASH
- 1KB User EEPROM
- 512B Internal AUX. RAM
- 256B Internal RAM
- Operating Voltage : 1.8V ~ 3.6V
- Operating Temperature : -40¡É ~ 85¡É
- Operating Frequency
- Max. 48MHz @ VDD = 3.0V
- Max. Programmable 21 I/O Pins
- Push-Pull Control, Open drain, Push-Pull Output - TTL and CMOS compatible logic levels
- Low Voltage Detector (1.6V)
- Internal RING OSC with Calibration function
- 48MHz @ VDD = 3V (±3%) - 32kHz @ VDD = 1.62V (±10%) (Low Power Osc)
- Supporting ISP / IAP / MDS
- 10-channel Touch Sensing (24-MLF/32-MLF)
- Capacitance sensing - Digital sensing - 16bit level resolution
- Three 16-bit Timer/Counters
- 2-Channel I2C (Master/Slave)
- 1-channel SPI (Master/Slave)
- 1-channel UART
- Max. 8-channel 8bit high speed PWM for DIMMING (32-MLF)
- Max. 4-channel 8bit high speed PWM for DIMMING (24-MLF)
- 15 Interrupt Sources
- Timer0/1/2, WDT, LVD, I2C, SPI, PWM, TS - 5 External Source : both edge/level - Two-level interrupt priority
- Power Down Wake-up Sources
- Reset Sources + 5 External interrupt (both lvevls) - WDT interrupt
- Reset Sources
- On-chip POR (Power-On-Reset) - External reset - LVD (Low Voltage Detector) Reset - WDT (Watchdog Timer) Reset
- Power Consumption
- active current : Max 1mA @3.3V, 2MHz - idle current : Max 0.5mA @3.3V, 2MHz - stop current : Max 60uA @3.3V
- E.S.D. Protection Up to
- 8000V for Touch Sensor Channel Pin - 2000V for Normal I/O Pin
- Latch-up Protection Up to ±200mA
- Package
- 24-MLF
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