/*-------------------------------------------------------------------------- TOUCHCORE20.H (ver 0.1) Header file for the GenCore Turbo TOUCHCORE2.0, TOUCHCORE2.1 Copyright (c) 2003-2008 CORERIVER Semiconductor. All rights reserved. --------------------------------------------------------------------------*/ #ifndef TC20_HEADER_FILE #define TC20_HEADER_FILE 1 /*------------------------------------------------ Byte Registers ------------------------------------------------*/ sfr P0 = 0x80; sfr SP = 0x81; sfr DPL = 0x82; sfr DPH = 0x83; sfr ALTSEL2 = 0x84; sfr ALTSEL = 0x85; sfr CKSEL = 0x86; sfr PCON = 0x87; sfr TCON = 0x88; sfr TMOD = 0x89; sfr TL0 = 0x8A; sfr TL1 = 0x8B; sfr TH0 = 0x8C; sfr TH1 = 0x8D; sfr CKCON = 0x8E; sfr RINGCON = 0x8F; sfr P1 = 0x90; sfr EXIF = 0x91; sfr PWM0CON = 0x92; sfr PWM0CNT = 0x93; sfr PWM0D0 = 0x94; sfr PWM0D1 = 0x95; sfr PWM0D2 = 0x96; sfr PWM0D3 = 0x97; sfr SCON = 0x98; sfr SBUF = 0x99; sfr PWM0OEN = 0x9B; sfr PWM0D4 = 0x9C; sfr PWM0D5 = 0x9D; sfr PWM0D6 = 0x9E; sfr PWM0D7 = 0x9F; sfr P2 = 0xA0; sfr EIE = 0xA1; sfr PWM1CON = 0xA2; sfr PWM1CNT = 0xA3; sfr PWM1D0 = 0xA4; sfr PWM1D1 = 0xA5; sfr PWM1D2 = 0xA6; sfr PWM1D3 = 0xA7; sfr IE = 0xA8; sfr SADDR = 0xA9; sfr PWM1OEN = 0xAB; sfr PWM1D4 = 0xAC; sfr PWM1D5 = 0xAD; sfr PWM1D6 = 0xAE; sfr PWM1D7 = 0xAF; sfr P3 = 0xB0; sfr EIP = 0xB1; sfr IT = 0xB2; sfr P4 = 0xB3; sfr SPICON = 0xB4; sfr SPICK = 0xB5; sfr SPIDR = 0xB6; sfr IPH = 0xB7; sfr IP = 0xB8; sfr SADEN = 0xB9; sfr ITSEL = 0xBA; sfr SPIST = 0xC0; sfr TSCON = 0xC1; sfr TSCFG = 0xC2; sfr TSCLK = 0xC3; sfr PMR = 0xC4; sfr STATUS = 0xC5; sfr OSCICN = 0xC6; sfr TSOSCICN = 0xC7; sfr T2CON = 0xC8; sfr T2MOD = 0xC9; sfr RCAP2L = 0xCA; sfr RCAP2H = 0xCB; sfr TL2 = 0xCC; sfr TH2 = 0xCD; sfr ADCENB0 = 0xCE; sfr ADCENB1 = 0xCF; sfr PSW = 0xD0; sfr P0SEL = 0xD1; sfr P1SEL = 0xD2; sfr P2SEL = 0xD3; sfr P3SEL = 0xD4; sfr P4SEL = 0xD5; sfr ADCENB2 = 0xD6; sfr ADCENB3 = 0xD7; sfr WDCON = 0xD8; sfr P0TYPE = 0xD9; sfr P1TYPE = 0xDA; sfr P2TYPE = 0xDB; sfr P3TYPE = 0xDC; sfr P4TYPE = 0xDD; sfr ADCON = 0xDE; sfr ADCSEL = 0xDF; sfr ACC = 0xE0; sfr P0DIR = 0xE1; sfr P1DIR = 0xE2; sfr P2DIR = 0xE3; sfr P3DIR = 0xE4; sfr P4DIR = 0xE5; sfr ADCR = 0xE6; sfr I2CST = 0xE8; sfr I2CCON = 0xE9; sfr I2CCFG = 0xEA; sfr I2CSLA = 0xEB; sfr I2CDAT = 0xEC; sfr I2CSCL = 0xED; sfr B = 0xF0; sfr EECNTLD = 0xF1; sfr EECNTL = 0xF2; sfr EECNTM = 0xF3; sfr EECON = 0xF6; sfr EEAEN = 0xF7; /*------------------------------------------------ P0 (80h) Bit Register ------------------------------------------------*/ sbit P0_0 = 0x80; sbit P0_1 = 0x81; sbit P0_2 = 0x82; sbit P0_3 = 0x83; sbit P0_4 = 0x84; sbit P0_5 = 0x85; sbit P0_6 = 0x86; sbit P0_7 = 0x87; /*------------------------------------------------ TCON (88h) Bit Register ------------------------------------------------*/ sbit IT0 = 0x88; // External interrupt 0 level/edge trigger control (Edge detect(IT0=1)/Level detect(IT0=0;default)) sbit IE0 = 0x89; // External interrupt 0 flag sbit IT1 = 0x8A; // External interrupt 1 level/edge trigger control (Edge detect(IT0=1)/Level detect(IT0=0;default)) sbit IE1 = 0x8B; // External interrupt 1 flag sbit TR0 = 0x8C; // Timer 0 run control sbit TF0 = 0x8D; // Timer 0 overflow flag sbit TR1 = 0x8E; // Timer 1 run control sbit TF1 = 0x8F; // Timer 1 overflow flag /*------------------------------------------------ P1 (90h) Bit Register ------------------------------------------------*/ sbit P1_0 = 0x90; sbit P1_1 = 0x91; sbit P1_2 = 0x92; sbit P1_3 = 0x93; sbit P1_4 = 0x94; sbit P1_5 = 0x95; sbit P1_6 = 0x96; sbit P1_7 = 0x97; /*------------------------------------------------ SCON (98h) Bit Register ------------------------------------------------*/ sbit RI = 0x98; // Reception Interrupt Flag. Must be cleared by S/W sbit TI = 0x98; // Transmission Interrupt Flag. Must be cleared by S/W sbit RB8 = 0x9A; // 9th data bit that was received in Mode 2 and 3 // In mode 1, the validity of a Stop Bit is checked if SM2=1 // In mode 0, SM2 should be 0 sbit TB8 = 0x9B; // 9th data bit that will be transmitted in Mode 2 and 3 sbit REN = 0x9C; // Enable/Disable Reception sbit SM2 = 0x9D; // Enable the Automatic Address Recongnition in Mode 2 and 3 sbit SM1 = 0x9E; // Serial Port Operating Mode Selection sbit SM0 = 0x9F; // Serial Port Operation Mode Selection /*------------------------------------------------ P2 (A0h) Bit Register ------------------------------------------------*/ sbit P2_0 = 0xA0; sbit P2_1 = 0xA1; sbit P2_2 = 0xA2; sbit P2_3 = 0xA3; sbit P2_4 = 0xA4; sbit P2_5 = 0xA5; sbit P2_6 = 0xA6; sbit P2_7 = 0xA7; /*------------------------------------------------ IE (A8) Bit Register ------------------------------------------------*/ sbit EX0 = 0xA8; // External interrupt 0 enable sbit ET0 = 0xA9; // Timer 0 interrupt enable sbit EX1 = 0xAA; // External interrupt 1 enable sbit ET1 = 0xAB; // Timer 1 interrupt enable sbit ES = 0xAC; // Serial port interrupt enable sbit ET2 = 0xAD; // Timer 2 interrupt enable sbit EADC = 0xAE; // ADC interrupt enable sbit EA = 0xAF; // Enable/Disable all interrupts /*------------------------------------------------ P3 (B0h) Bit Register ------------------------------------------------*/ sbit P3_0 = 0xB0; sbit P3_1 = 0xB1; sbit P3_2 = 0xB2; sbit P3_3 = 0xB3; sbit P3_4 = 0xB4; sbit P3_5 = 0xB5; sbit P3_6 = 0xB6; sbit P3_7 = 0xB7; /*------------------------------------------------ IP (B8h) Bit Register ------------------------------------------------*/ sbit PX0 = 0xB8; // External interrupt 0 priority low sbit PT0 = 0xB9; // Timer 0 interrupt priority low sbit PX1 = 0xBA; // External interrupt 1 priority low sbit PT1 = 0xBB; // Timer 1 interrupt priority low sbit PS = 0xBC; // Serial port(UART) interrupt priority low sbit PT2 = 0xBD; // Timer 2 interrupt priority low sbit PADC = 0xBE; // ADC interrupt priority low /*------------------------------------------------ SPIST (C0h) Bit Register ------------------------------------------------*/ sbit SPIOF = 0xC0; // SPI Read Overflow Flag // [1]If a new data is received while SPIDR is still holding the previous data, the flag is set // SPIF must be cleared before receiving a data again sbit SPICOL = 0xC1; // SPI Write Collision Flag // [1]SPIDR is Written when TXBV is set. The previous data is lost sbit SPIF = 0xC2; // SPI Interrupt Flag // [1]Serial transfer is complete. If SPIE is set and EA is set, SPI interrupt is generated sbit TXBV = 0xC3; // TX buffer of SPIDR holds valid data // [1]Set by H/W when user write SPIDR while SPI is enabled // [0]Cleared by H/W when the data is moved to TX shift register or SPI is disabled /*------------------------------------------------ T2CON (C8h) Bit Register ------------------------------------------------*/ sbit CPRL2 = 0xC8; // Capture/Reload flag sbit CT2 = 0xC9; // Timer or Counter Selection. If C/T2=0, Timer Operation sbit TR2 = 0xCA; // Timer 2 Run Control sbit EXEN2 = 0xCB; // Timer 2 External Enable flag sbit TCLK = 0xCC; // Trasmit Clock flag sbit RCLK = 0xCD; // Receive Clock flag sbit EXF2 = 0xCE; // Timer 2 External flag sbit TF2 = 0xCF; // Timer 2 Overflow flag /*------------------------------------------------ PSW (D0h) Bit Register ------------------------------------------------*/ sbit p = 0xD0; // Parity bit. Set/clear by H/W according to ACC odd parity sbit F1 = 0xD1; // User flag 1 sbit OV = 0xD2; // Overflow flag sbit RS0 = 0xD3; // Register bank select [0,0]Bank0, [0,1]Bank1 sbit RS1 = 0xD4; // Register bank select [1,0]Bank2, [1,1]Bank3 sbit F0 = 0xD5; // User flag 0 sbit AC = 0xD6; // Auxiliary carry flag sbit CY = 0xD7; // Carry flag /*------------------------------------------------ WDCON (D8h) Bit Register ------------------------------------------------*/ sbit RWT = 0xD8; // Restart Watchdog Timer sbit EWT = 0xD9; // Watchdog Timer Reset Enable sbit WTRF = 0xDA; // Watchdog Timer Reset Flag. Only cleared by S/W sbit WDIF = 0xDB; // Watchdog Timer Interrupt Flag sbit PFI = 0xDC; // Poser-Fail interrupt Flag (always 1 @ 3V operation) sbit EPFI = 0xDD; // Enable Poser-fail Interrupt sbit POR = 0xDE; // Power-on Reset Flag sbit WDMOD = 0xDF; // WDT mode selection flag /*------------------------------------------------ ACC (E0h) Bit Register ------------------------------------------------*/ sbit ACC0 = 0xE0; sbit ACC1 = 0xE1; sbit ACC2 = 0xE2; sbit ACC3 = 0xE3; sbit ACC4 = 0xE4; sbit ACC5 = 0xE5; sbit ACC6 = 0xE6; sbit ACC7 = 0xE7; /*------------------------------------------------ I2CST (E8h) Bit Register ------------------------------------------------*/ sbit I2CBF = 0xE8; // Busy flag in slave&master mode // [0]RX not complete(Receive), TX not complete(Transmitter) // [1]RX complite(Recieve), TX complite(Transmitter) sbit I2CS = 0xE9; // Start flag in slave&master mode // [0]Indicates Start bit was not detected // [1]Indecates Start bit was detected sbit I2CP = 0xEA; // Stop flag in slave&master mode // [0]Indicates Stop bit was not detected // [1]Indicates Stop bit was detected sbit I2CDA = 0xEB; // Data/Address flag in slave mode // [0]Indecates the last byte received or transmitted was Data // [1]Indecates the last byte received or transmitted was Address sbit I2CRW = 0xEC; // I2C Read/Write flag in slave mode // [0]Write state, [1]Read state sbit I2CACK = 0xED; // I2C Acknowledge flag in slave&master mode // [0]Indicate receiving Acknowledge bit // [1]Indecate receiving Not Acknwledge bit sbit I2COF = 0xEE; // I2C Overflow Flag in slave&master // [0]Idle, [1]Overflow occurred sbit I2CIF = 0xEF; // I2C Master Interrupt Flag in slave&master mode // [0]Idel, [1]Interrupt occurred /*------------------------------------------------ B (F0h) Bit Register ------------------------------------------------*/ sbit B0 = 0xF0; sbit B1 = 0xF1; sbit B2 = 0xF2; sbit B3 = 0xF3; sbit B4 = 0xF4; sbit B5 = 0xF5; sbit B6 = 0xF6; sbit B7 = 0xF7; /*------------------------------------------------ P0 (80h) Bit Register ------------------------------------------------*/ #define P0_0_ 0x01 #define P0_1_ 0x02 #define P0_2_ 0x04 #define P0_3_ 0x08 #define P0_4_ 0x10 #define P0_5_ 0x20 #define P0_6_ 0x40 #define P0_7_ 0x80 /*------------------------------------------------ SP (81h) Bit Register ------------------------------------------------*/ #define SP0_ 0x01 #define SP1_ 0x02 #define SP2_ 0x04 #define SP3_ 0x08 #define SP4_ 0x10 #define SP5_ 0x20 #define SP6_ 0x40 #define SP7_ 0x80 /*------------------------------------------------ DPL (82h) Bit Register ------------------------------------------------*/ #define DPL0_ 0x01 #define DPL1_ 0x02 #define DPL2_ 0x04 #define DPL3_ 0x08 #define DPL4_ 0x10 #define DPL5_ 0x20 #define DPL6_ 0x40 #define DPL7_ 0x80 /*------------------------------------------------ DPH (83h) Bit Register ------------------------------------------------*/ #define DPH0_ 0x01 #define DPH1_ 0x02 #define DPH2_ 0x04 #define DPH3_ 0x08 #define DPH4_ 0x10 #define DPH5_ 0x20 #define DPH6_ 0x40 #define DPH7_ 0x80 /*------------------------------------------------ ALTSEL2 (84h) Bit Register ------------------------------------------------*/ #define INT_A_ 0x01 #define I2C_A_ 0x02 #define SPIC_A_ 0x04 #define SPID_A_ 0x08 #define UART_A_ 0x10 #define UART_B_ 0x20 #define PWM_A_ 0x40 /*------------------------------------------------ ALTSEL (85h) Bit Register ------------------------------------------------*/ #define RST_IOEN_ 0x01 #define XTAL_IOEN_ 0x02 #define EA_IOEN_ 0x04 /*------------------------------------------------ CKSEL (86h) Bit Register ------------------------------------------------*/ #define R32KEN_ 0x01 #define RGPR_ 0x02 #define TS_XTRG_ 0x04 #define R24MOE_ 0x08 #define R32KOE_ 0x10 /*------------------------------------------------ PCON (87h) Bit Values ------------------------------------------------*/ #define IDL_ 0x01 #define PD_ 0x02 #define GF0_ 0x04 #define GF1_ 0x08 #define POF_ 0x10 #define SMOD0_ 0x40 #define SMOD1_ 0x80 /*------------------------------------------------ TCON (88h)Bit Register ------------------------------------------------*/ #define IT0_ 0x01 #define IE0_ 0x02 #define IT1_ 0x04 #define IE1_ 0x08 #define TR0_ 0x10 #define TF0_ 0x20 #define TR1_ 0x40 #define TF1_ 0x80 /*------------------------------------------------ TMOD (89h) Bit Values ------------------------------------------------*/ #define M0_ 0x01 #define M1_ 0x02 #define CT0_ 0x04 #define GATE0_ 0x08 #define M2_ 0x10 #define M3_ 0x20 #define CT1_ 0x40 #define GATE1_ 0x80 /*------------------------------------------------ TL0 (8Ah) Bit Register ------------------------------------------------*/ #define TL0_0_ 0x01 #define TL0_1_ 0x02 #define TL0_2_ 0x04 #define TL0_3_ 0x08 #define TL0_4_ 0x10 #define TL0_5_ 0x20 #define TL0_6_ 0x40 #define TL0_7_ 0x80 /*------------------------------------------------ TL1 (8Bh) Bit Register ------------------------------------------------*/ #define TL1_0_ 0x01 #define TL1_1_ 0x02 #define TL1_2_ 0x04 #define TL1_3_ 0x08 #define TL1_4_ 0x10 #define TL1_5_ 0x20 #define TL1_6_ 0x40 #define TL1_7_ 0x80 /*------------------------------------------------ TH0 (8Ch) Bit Register ------------------------------------------------*/ #define TH0_0_ 0x01 #define TH0_1_ 0x02 #define TH0_2_ 0x04 #define TH0_3_ 0x08 #define TH0_4_ 0x10 #define TH0_5_ 0x20 #define TH0_6_ 0x40 #define TH0_7_ 0x80 /*------------------------------------------------ TH1 (8Dh) Bit Register ------------------------------------------------*/ #define TH1_0_ 0x01 #define TH1_1_ 0x02 #define TH1_2_ 0x04 #define TH1_3_ 0x08 #define TH1_4_ 0x10 #define TH1_5_ 0x20 #define TH1_6_ 0x40 #define TH1_7_ 0x80 /*------------------------------------------------ CKCON (8Eh) Bit Register ------------------------------------------------*/ #define T0M_ 0x04 #define T1M_ 0x08 #define T2M_ 0x10 #define WD0_ 0x20 #define WD1_ 0x40 #define WD2_ 0x80 /*------------------------------------------------ RINGCON (8Fh) Bit Register ------------------------------------------------*/ #define S0_ 0x01 #define S1_ 0x02 #define S2_ 0x04 #define S3_ 0x08 #define S4_ 0x10 #define S5_ 0x20 #define S6_ 0x40 #define S7_ 0x80 /*------------------------------------------------ P1 (90h) Bit Register ------------------------------------------------*/ #define P1_0_ 0x01 #define P1_1_ 0x02 #define P1_2_ 0x04 #define P1_3_ 0x08 #define P1_4_ 0x10 #define P1_5_ 0x20 #define P1_6_ 0x40 #define P1_7_ 0x80 /*------------------------------------------------ EXIF (91h) Bit Register ------------------------------------------------*/ #define BGS_ 0x01 /* Band-gap Select. When set, LVD will run in power-down mode. */ #define RGSL_ 0x02 /* When wakeup from power down mode in XTAL clock, use RING oscillator as system clock during 65,536 XTAL clocks */ #define RGMD_ 0x04 /* RING mode */ #define XTRG_ 0x08 /* Crystal Select. Read only*/ #define IE2_ 0x10 /* External Interrupt 2 Flag */ #define IE3_ 0x20 /* External Interrupt 3 Flag_b */ #define IE4_ 0x40 #define IE5_ 0x80 /*------------------------------------------------ PWM0CON (92h) Bit Register PWM1CON (A2h) Bit Register ------------------------------------------------*/ #define PWMEN_ 0x01 #define PWMOVF_ 0x02 #define CPS0_ 0x10 #define CPS1_ 0x20 #define CPS2_ 0x40 /*------------------------------------------------ PWM0CNT (93h) Bit Register PWM1CNT (A3h) Bit Register ------------------------------------------------*/ #define CNT0_ 0x01 #define CNT1_ 0x02 #define CNT2_ 0x04 #define CNT3_ 0x08 #define CNT4_ 0x10 #define CNT5_ 0x20 #define CNT6_ 0x40 #define CNT7_ 0x80 /*------------------------------------------------ PWM0D0 (94h) Bit Register PWM0D1 (95h) Bit Register PWM0D2 (96h) Bit Register PWM0D3 (97h) Bit Register PWM0D4 (9Ch) Bit Register PWM0D5 (9Dh) Bit Register PWM0D6 (9Eh) Bit Register PWM0D7 (9Fh) Bit Register PWM1D0 (A4h) Bit Register PWM1D1 (A5h) Bit Register PWM1D2 (A6h) Bit Register PWM1D3 (A7h) Bit Register PWM1D4 (ACh) Bit Register PWM1D5 (ADh) Bit Register PWM1D6 (AEh) Bit Register PWM1D7 (AFh) Bit Register ------------------------------------------------*/ #define PWMD0 0x01 #define PWMD1_ 0x02 #define PWMD2_ 0x04 #define PWMD3_ 0x08 #define PWMD4_ 0x10 #define PWMD5_ 0x20 #define PWMD6_ 0x40 #define PWMD7_ 0x80 /*------------------------------------------------ SCON(98h) Bit Register ------------------------------------------------*/ #define RI_ 0x01 #define TI_ 0x02 #define RB8_ 0x04 #define TB8_ 0x08 #define REN_ 0x10 #define SM2_ 0x20 #define SM1_ 0x40 #define SM0_ 0x80 /*------------------------------------------------ SBUF (99h) Bit Register ------------------------------------------------*/ #define SBUF0_ 0x01 #define SBUF1_ 0x02 #define SBUF2_ 0x04 #define SBUF3_ 0x08 #define SBUF4_ 0x10 #define SBUF5_ 0x20 #define SBUF6_ 0x40 #define SBUF7_ 0x80 /*------------------------------------------------ PWM0OEN (9Bh) Bit Register PWM1OEN (ABh) Bit Register ------------------------------------------------*/ #define OE0_ 0x01 #define OE1_ 0x02 #define OE2_ 0x04 #define OE3_ 0x08 #define OE4_ 0x10 #define OE5_ 0x20 #define OE6_ 0x40 #define OE7_ 0x80 /*------------------------------------------------ P2 (A0h) Bit Register ------------------------------------------------*/ #define P2_0_ 0x01 #define P2_1_ 0x02 #define P2_2_ 0x04 #define P2_3_ 0x08 #define P2_4_ 0x10 #define P2_5_ 0x20 #define P2_6_ 0x40 #define P2_7_ 0x80 /*------------------------------------------------ EIE (A1h) Bit Register ------------------------------------------------*/ #define EX2_ 0x01 #define EX3_ 0x02 #define EX4_ 0x04 #define EX5_ 0x08 #define EWDT_ 0x10 #define EI2C_ 0x20 #define ESPI_ 0x80 /*------------------------------------------------ IE (A8h) Bit Register ------------------------------------------------*/ #define EX0_ 0x01 #define ET0_ 0x02 #define EX1_ 0x04 #define ET1_ 0x08 #define ES_ 0x10 #define ET2_ 0x20 #define EA_ 0x80 /*------------------------------------------------ SADDR (A9h) Bit Register ------------------------------------------------*/ #define SADDR0_ 0x01 #define SADDR1_ 0x02 #define SADDR2_ 0x04 #define SADDR3_ 0x08 #define SADDR4_ 0x10 #define SADDR5_ 0x20 #define SADDR6_ 0x40 #define SADDR7_ 0x80 /*------------------------------------------------ P3 (B0h) Bit Register ------------------------------------------------*/ #define P3_0_ 0x01 #define P3_1_ 0x02 #define P3_2_ 0x04 #define P3_3_ 0x08 #define P3_4_ 0x10 #define P3_5_ 0x20 #define P3_6_ 0x40 #define P3_7_ 0x80 /*------------------------------------------------ EIP (B1h) Bit Register ------------------------------------------------*/ #define PX2_ 0x01 #define PX3_ 0x02 #define PX4_ 0x04 #define PX5_ 0x08 #define PWDT_ 0x10 #define PI2C_ 0x20 #define PSPI_ 0x80 /*------------------------------------------------ IT (B2h) Bit Register ------------------------------------------------*/ #define IT2_ 0x01 #define IT3_ 0x02 #define IT4_ 0x04 #define IT5_ 0x08 /*------------------------------------------------ P4 (B3h) Bit Register ------------------------------------------------*/ #define P4_0_ 0x01 #define P4_1_ 0x02 #define P4_2_ 0x04 #define P4_3_ 0x08 #define P4_4_ 0x10 #define P4_5_ 0x20 #define P4_6_ 0x40 #define P4_7_ 0x80 /*------------------------------------------------ SPICON (B4h) Bit Register ------------------------------------------------*/ #define SPIEN_ 0x01 #define SPIOEN_ 0x02 #define CKPHA_ 0x04 #define CKPOL_ 0x08 #define MSSEL_ 0x10 #define BORD_ 0x20 #define MODE_ 0x40 /*------------------------------------------------ SPICK (B5h) Bit Register ------------------------------------------------*/ #define SPICK0_ 0x01 #define SPICK1_ 0x02 #define SPICK2_ 0x04 /*------------------------------------------------ SPIDR (B6h) Bit Register ------------------------------------------------*/ #define DATA0_ 0x01 #define DATA1_ 0x02 #define DATA2_ 0x04 #define DATA3_ 0x08 #define DATA4_ 0x10 #define DATA5_ 0x20 #define DATA6_ 0x40 #define DATA7_ 0x80 /*------------------------------------------------ IPH (B7h) Bit Register ------------------------------------------------*/ #define PX0H_ 0x01 #define PT0H_ 0x02 #define PX1H_ 0x04 #define PT1H_ 0x08 #define PSH_ 0x10 #define PT2H_ 0x20 #define PADCH_ 0x40 /*------------------------------------------------ IP (B8h) Bit Register ------------------------------------------------*/ #define PX0_ 0x01 #define PT0_ 0x02 #define PX1_ 0x04 #define PT1_ 0x08 #define PS_ 0x10 #define PT2_ 0x20 #define PADC_ 0x40 /*------------------------------------------------ SADEN (B9h) Bit Register ------------------------------------------------*/ #define SADEN0_ 0x01 #define SADEN1_ 0x02 #define SADEN2_ 0x04 #define SADEN3_ 0x08 #define SADEN4_ 0x10 #define SADEN5_ 0x20 #define SADEN6_ 0x40 #define SADEN7_ 0x80 /*------------------------------------------------ ITSEL (BAh) Bit Register ------------------------------------------------*/ #define ITSEL0_ 0x01 #define ITSEL1_ 0x02 #define ITSEL2_ 0x04 #define ITSEL3_ 0x08 #define ITSEL4_ 0x10 #define ITSEL5_ 0x20 /*------------------------------------------------ SPIST (C0h) Bit Register ------------------------------------------------*/ #define SPIOF_ 0x01 #define SPICOL_ 0x02 #define SPIF_ 0x04 #define TXBV_ 0x08 /*------------------------------------------------ TSCON (C1h) Bit Register ------------------------------------------------*/ #define TS_RUN_ 0x01 #define TSIF_ 0x02 #define TS_CNT_CLR_ 0x04 /*------------------------------------------------ TSCFG (C2h) Bit Register ------------------------------------------------*/ #define ETS_ 0x01 #define PTS_ 0x02 /*------------------------------------------------ TSCLK (C3h)Bit Register ------------------------------------------------*/ #define TSRCK0_ 0x01 #define TSRCK1_ 0x02 #define TSRCK2_ 0x04 #define TSRCK3_ 0x08 /*------------------------------------------------ PMR (C4h)Bit Register ------------------------------------------------*/ #define ALEOFF_ 0x04 #define XTOFF_ 0x08 /*------------------------------------------------ STATUS (C5h)Bit Register ------------------------------------------------*/ #define XTUP_ 0x10 /*------------------------------------------------ OSCICN (C6h)Bit Register ------------------------------------------------*/ #define DIV0_ 0x01 #define DIV1_ 0x02 #define RINGON_ 0x04 #define DIV2_ 0x08 /*------------------------------------------------ TSOSCICN (C7h)Bit Register ------------------------------------------------*/ #define TSRDIV0_ 0x01 #define TSRDIV1_ 0x02 #define TSRINGON_ 0x04 #define TSRDIV2_ 0x08 /*------------------------------------------------ T2CON (C8h)Bit Register ------------------------------------------------*/ #define CPRL2_ 0x01 #define CT2_ 0x02 #define TR2_ 0x04 #define EXEN2_ 0x08 #define TCLK_ 0x10 #define RCLK_ 0x20 #define EXF2_ 0x40 #define TF2_ 0x80 /*------------------------------------------------ T2MOD (C9h)Bit Register ------------------------------------------------*/ #define DCEN_ 0x01 #define T2OE_ 0x02 /*------------------------------------------------ RCAP2L (CAh) Bit Register ------------------------------------------------*/ #define RCAP2L_0_ 0x01 #define RCAP2L_1_ 0x02 #define RCAP2L_2_ 0x04 #define RCAP2L_3_ 0x08 #define RCAP2L_4_ 0x10 #define RCAP2L_5_ 0x20 #define RCAP2L_6_ 0x40 #define RCAP2L_7_ 0x80 /*------------------------------------------------ RCAP2H (CBh) Bit Register ------------------------------------------------*/ #define RCAP2H_0_ 0x01 #define RCAP2H_1_ 0x02 #define RCAP2H_2_ 0x04 #define RCAP2H_3_ 0x08 #define RCAP2H_4_ 0x10 #define RCAP2H_5_ 0x20 #define RCAP2H_6_ 0x40 #define RCAP2H_7_ 0x80 /*------------------------------------------------ TL2 (CCh) Bit Register ------------------------------------------------*/ #define TL2_0_ 0x01 #define TL2_1_ 0x02 #define TL2_2_ 0x04 #define TL2_3_ 0x08 #define TL2_4_ 0x10 #define TL2_5_ 0x20 #define TL2_6_ 0x40 #define TL2_7_ 0x80 /*------------------------------------------------ TH2 (CDh) Bit Register ------------------------------------------------*/ #define TH2_0_ 0x01 #define TH2_1_ 0x02 #define TH2_2_ 0x04 #define TH2_3_ 0x08 #define TH2_4_ 0x10 #define TH2_5_ 0x20 #define TH2_6_ 0x40 #define TH2_7_ 0x80 /*------------------------------------------------ ADCENB0 (CEh) Bit Register ------------------------------------------------*/ #define ADCENB0_0_ 0x01 #define ADCENB0_1_ 0x02 #define ADCENB0_2_ 0x04 #define ADCENB0_3_ 0x08 #define ADCENB0_4_ 0x10 #define ADCENB0_5_ 0x20 #define ADCENB0_6_ 0x40 #define ADCENB0_7_ 0x80 /*------------------------------------------------ ADCENB1 (CFh) Bit Register ------------------------------------------------*/ #define ADCENB1_0_ 0x01 #define ADCENB1_1_ 0x02 #define ADCENB1_2_ 0x04 #define ADCENB1_3_ 0x08 #define ADCENB1_4_ 0x10 #define ADCENB1_5_ 0x20 #define ADCENB1_6_ 0x40 #define ADCENB1_7_ 0x80 /*------------------------------------------------ P0SEL (D1h) Bit Register ------------------------------------------------*/ #define P0SEL_0_ 0x01 #define P0SEL_1_ 0x02 #define P0SEL_2_ 0x04 #define P0SEL_3_ 0x08 #define P0SEL_4_ 0x10 #define P0SEL_5_ 0x20 #define P0SEL_6_ 0x40 #define P0SEL_7_ 0x80 /*------------------------------------------------ P1SEL (D2h) Bit Register ------------------------------------------------*/ #define P1SEL_0_ 0x01 #define P1SEL_1_ 0x02 #define P1SEL_2_ 0x04 #define P1SEL_3_ 0x08 #define P1SEL_4_ 0x10 #define P1SEL_5_ 0x20 #define P1SEL_6_ 0x40 #define P1SEL_7_ 0x80 /*------------------------------------------------ P2SEL (D3h) Bit Register ------------------------------------------------*/ #define P2SEL_0_ 0x01 #define P2SEL_1_ 0x02 #define P2SEL_2_ 0x04 #define P2SEL_3_ 0x08 #define P2SEL_4_ 0x10 #define P2SEL_5_ 0x20 #define P2SEL_6_ 0x40 #define P2SEL_7_ 0x80 /*------------------------------------------------ P3SEL (D4h) Bit Register ------------------------------------------------*/ #define P3SEL_0_ 0x01 #define P3SEL_1_ 0x02 #define P3SEL_2_ 0x04 #define P3SEL_3_ 0x08 #define P3SEL_4_ 0x10 #define P3SEL_5_ 0x20 #define P3SEL_6_ 0x40 #define P3SEL_7_ 0x80 /*------------------------------------------------ P4SEL (D5h) Bit Register ------------------------------------------------*/ #define P4SEL_0_ 0x01 #define P4SEL_1_ 0x02 #define P4SEL_2_ 0x04 #define P4SEL_3_ 0x08 #define P4SEL_4_ 0x10 #define P4SEL_5_ 0x20 #define P4SEL_6_ 0x40 #define P4SEL_7_ 0x80 /*------------------------------------------------ ADCENB2 (D6h) Bit Register ------------------------------------------------*/ #define ADCENB2_0_ 0x01 #define ADCENB2_1_ 0x02 #define ADCENB2_2_ 0x04 #define ADCENB2_3_ 0x08 #define ADCENB2_4_ 0x10 #define ADCENB2_5_ 0x20 #define ADCENB2_6_ 0x40 #define ADCENB2_7_ 0x80 /*------------------------------------------------ ADCENB3 (D7h) Bit Register ------------------------------------------------*/ #define ADCENB3_0_ 0x01 #define ADCENB3_1_ 0x02 #define ADCENB3_2_ 0x04 #define ADCENB3_3_ 0x08 #define ADCENB3_4_ 0x10 #define ADCENB3_5_ 0x20 #define ADCENB3_6_ 0x40 #define ADCENB3_7_ 0x80 /*------------------------------------------------ WDCON (D8h) Bit Register ------------------------------------------------*/ #define RWT_ 0x01 #define EWT_ 0x02 #define WTRF_ 0x04 #define WDIF_ 0x08 #define PFI_ 0x10 #define EPFI_ 0x20 #define POR_ 0x40 /*------------------------------------------------ P0TYPE (D9h) Bit Register ------------------------------------------------*/ #define P0TYPE_0_ 0x01 #define P0TYPE_1_ 0x02 #define P0TYPE_2_ 0x04 #define P0TYPE_3_ 0x08 #define P0TYPE_4_ 0x10 #define P0TYPE_5_ 0x20 #define P0TYPE_6_ 0x40 #define P0TYPE_7_ 0x80 /*------------------------------------------------ P1TYPE (DAh) Bit Register ------------------------------------------------*/ #define P1TYPE_0_ 0x01 #define P1TYPE_1_ 0x02 #define P1TYPE_2_ 0x04 #define P1TYPE_3_ 0x08 #define P1TYPE_4_ 0x10 #define P1TYPE_5_ 0x20 #define P1TYPE_6_ 0x40 #define P1TYPE_7_ 0x80 /*------------------------------------------------ P2TYPE (DBh) Bit Register ------------------------------------------------*/ #define P2TYPE_0_ 0x01 #define P2TYPE_1_ 0x02 #define P2TYPE_2_ 0x04 #define P2TYPE_3_ 0x08 #define P2TYPE_4_ 0x10 #define P2TYPE_5_ 0x20 #define P2TYPE_6_ 0x40 #define P2TYPE_7_ 0x80 /*------------------------------------------------ P3TYPE (DCh) Bit Register ------------------------------------------------*/ #define P3TYPE_0_ 0x01 #define P3TYPE_1_ 0x02 #define P3TYPE_2_ 0x04 #define P3TYPE_3_ 0x08 #define P3TYPE_4_ 0x10 #define P3TYPE_5_ 0x20 #define P3TYPE_6_ 0x40 #define P3TYPE_7_ 0x80 /*------------------------------------------------ P4TYPE (DDh) Bit Register ------------------------------------------------*/ #define P4TYPE_0_ 0x01 #define P4TYPE_1_ 0x02 #define P4TYPE_2_ 0x04 #define P4TYPE_3_ 0x08 #define P4TYPE_4_ 0x10 #define P4TYPE_5_ 0x20 #define P4TYPE_6_ 0x40 #define P4TYPE_7_ 0x80 /*------------------------------------------------ ADCON (DEh) Bit Register ------------------------------------------------*/ #define SAR0_ 0x01 #define SAR1_ 0x02 #define ADCF_ 0x10 #define AD_END_ 0x20 #define AD_REQ_ 0x40 #define AD_EN_ 0x80 /*------------------------------------------------ ADCSEL (DFh) Bit Register ------------------------------------------------*/ #define ADCS0_ 0x01 #define ADCS1_ 0x02 #define ADCS2_ 0x04 #define ADCS3_ 0x08 #define ADCS4_ 0x10 #define ADIV0_ 0x20 #define ADIV1_ 0x40 #define ADIV2_ 0x80 /*------------------------------------------------ ACC (E0h)Bit Register ------------------------------------------------*/ #define ACC0_ 0x01 #define ACC1_ 0x02 #define ACC2_ 0x04 #define ACC3_ 0x08 #define ACC4_ 0x10 #define ACC5_ 0x20 #define ACC6_ 0x40 #define ACC7_ 0x80 /*------------------------------------------------ P0DIR (E1h) Bit Register ------------------------------------------------*/ #define P0DIR_0_ 0x01 #define P0DIR_1_ 0x02 #define P0DIR_2_ 0x04 #define P0DIR_3_ 0x08 #define P0DIR_4_ 0x10 #define P0DIR_5_ 0x20 #define P0DIR_6_ 0x40 #define P0DIR_7_ 0x80 /*------------------------------------------------ P1DIR (E2h) Bit Register ------------------------------------------------*/ #define P1DIR_0_ 0x01 #define P1DIR_1_ 0x02 #define P1DIR_2_ 0x04 #define P1DIR_3_ 0x08 #define P1DIR_4_ 0x10 #define P1DIR_5_ 0x20 #define P1DIR_6_ 0x40 #define P1DIR_7_ 0x80 /*------------------------------------------------ P2DIR (E3h) Bit Register ------------------------------------------------*/ #define P2DIR_0_ 0x01 #define P2DIR_1_ 0x02 #define P2DIR_2_ 0x04 #define P2DIR_3_ 0x08 #define P2DIR_4_ 0x10 #define P2DIR_5_ 0x20 #define P2DIR_6_ 0x40 #define P2DIR_7_ 0x80 /*------------------------------------------------ P3DIR (E4h) Bit Register ------------------------------------------------*/ #define P3DIR_0_ 0x01 #define P3DIR_1_ 0x02 #define P3DIR_2_ 0x04 #define P3DIR_3_ 0x08 #define P3DIR_4_ 0x10 #define P3DIR_5_ 0x20 #define P3DIR_6_ 0x40 #define P3DIR_7_ 0x80 /*------------------------------------------------ P4DIR (E5h) Bit Register ------------------------------------------------*/ #define P4DIR_0_ 0x01 #define P4DIR_1_ 0x02 #define P4DIR_2_ 0x04 #define P4DIR_3_ 0x08 #define P4DIR_4_ 0x10 #define P4DIR_5_ 0x20 #define P4DIR_6_ 0x40 #define P4DIR_7_ 0x80 /*------------------------------------------------ ADCR (E6h) Bit Register ------------------------------------------------*/ #define SAR2_ 0x01 #define SAR3_ 0x02 #define SAR4_ 0x04 #define SAR5_ 0x08 #define SAR6_ 0x10 #define SAR7_ 0x20 #define SAR8_ 0x40 #define SAR9_ 0x80 /*------------------------------------------------ I2CST (E8h) Bit Register ------------------------------------------------*/ #define I2CBF_ 0x01 #define I2CS_ 0x02 #define I2CP_ 0x04 #define I2CDA_ 0x08 #define I2CRW_ 0x10 #define I2CACK_ 0x20 #define I2COF_ 0x40 #define I2CIF_ 0x80 /*------------------------------------------------ I2CCON (E9h) Bit Register ------------------------------------------------*/ #define I2CEN_ 0x01 #define I2CIOEN_ 0x02 #define SGEN_ 0x04 #define PGEN_ 0x08 #define LASTB_ 0x10 #define SCLHD_ 0x20 #define SLA2ME_ 0x40 /*------------------------------------------------ I2CCFG (EAh) Bit Register ------------------------------------------------*/ #define GCE_ 0x01 #define SPIE_ 0x02 #define ADSEL_ 0x04 #define MSSEL_ 0x08 /*------------------------------------------------ I2CSLA (EBh) Bit Register ------------------------------------------------*/ #define SLA1_0_ 0x01 #define SLA1_1_ 0x02 #define SLA1_2_ 0x04 #define SLA1_3_ 0x08 #define SLA1_4_ 0x10 #define SLA1_5_ 0x20 #define SLA1_6_ 0x40 #define SLA1_7_ 0x80 /*------------------------------------------------ I2CDAT (ECh) Bit Register ------------------------------------------------*/ #define MDAT0_ 0x01 #define MDAT1_ 0x02 #define MDAT2_ 0x04 #define MDAT3_ 0x08 #define MDAT4_ 0x10 #define MDAT5_ 0x20 #define MDAT6_ 0x40 #define MDAT7_ 0x80 /*------------------------------------------------ I2CSCL (EDh) Bit Register ------------------------------------------------*/ #define MSCL0_ 0x01 #define MSCL1_ 0x02 #define MSCL2_ 0x04 #define MSCL3_ 0x08 #define MSCL4_ 0x10 #define MSCL5_ 0x20 #define MSCL6_ 0x40 #define MSCL7_ 0x80 /*------------------------------------------------ B (F0h) Bit Value ------------------------------------------------*/ #define B0_ 0x01 #define B1_ 0x02 #define B2_ 0x04 #define B3_ 0x08 #define B4_ 0x10 #define B5_ 0x20 #define B6_ 0x40 #define B7_ 0x80 /*------------------------------------------------ EECNTLD (F1h) Bit Register ------------------------------------------------*/ #define EECNTLD_ 0x80 /*------------------------------------------------ EECNTL (F2h) Bit Value ------------------------------------------------*/ #define EECNT0_ 0x01 #define EECNT1_ 0x02 #define EECNT2_ 0x04 #define EECNT3_ 0x08 #define EECNT4_ 0x10 #define EECNT5_ 0x20 #define EECNT6_ 0x40 #define EECNT7_ 0x80 /*------------------------------------------------ EECNTM (F3h) Bit Value ------------------------------------------------*/ #define EECNT8_ 0x01 #define EECNT9_ 0x02 #define EECNT10_ 0x04 #define EECNT11_ 0x08 #define EECNT12_ 0x10 #define EECNT13_ 0x20 #define EECNT14_ 0x40 #define EECNT15_ 0x80 /*------------------------------------------------ EECON (F6h) Bit Value ------------------------------------------------*/ #define EINIT_ 0x01 #define EWST_ 0x02 #define ECOMM_ 0x04 #define EWF_ 0x08 #define EDONE_ 0x10 #define EFLAG_ 0x40 /*------------------------------------------------ EEAEN (F7h) Bit Register ------------------------------------------------*/ #define EAEN_ 0x01 /*------------------------------------------------ Interrupt Vectors: Interrupt Address = (Number * 8) + 3 ------------------------------------------------*/ #define INT0_VECTOR 0 // 0x03 #define TF0_VECTOR 1 // 0x0B #define INT1_VECTOR 2 // 0x13 #define TF1_VECTOR 3 // 0x1B #define RITI_VECTOR 4 // 0x23 #define TF2_VECTOR 5 // 0x2B #define ADC_VECTOR 7 // 0x3B #define INT2_VECTOR 8 // 0x43 #define INT3_VECTOR 9 // 0x4B #define INT4_VECTOR 10 // 0x53 #define INT5_VECTOR 11 // 0x5B #define WDT_VECTOR 12 // 0x63 #define I2C_VECTOR 13 // 0x6B #define RESERVED_VECTOR 14 // 0x73 #define SPI_VECTOR 15 // 0x7B #define TS_VECTOR 16 // 0x83 /*------------------------------------------------ IAP Call function ------------------------------------------------*/ #define iap_eeprom_program 0xFF0A #define iap_eeprom_erase 0xFF00 /*------------------------------------------------ Register Banks ------------------------------------------------*/ #define REGISTER_BANK_0 0 /* Register Bank 0 */ #define REGISTER_BANK_1 1 /* Register Bank 1 */ #define REGISTER_BANK_2 2 /* Register Bank 2 */ #define REGISTER_BANK_3 3 /* Register Bank 3 */ /*----------------------------------------------*/ #endif