// ************************************************************************** // // This confidential and proprietary Header_file may be used only as // authorised by a licensing agreement from CORERIVER Semiconductor Co., Ltd. // // (c) Copyright 2008 CORERIVER Semiconductor Co., Ltd. // All Rights Reserved // // The entire notice above must be reproduced on all authorised // copies and copies may only be made to the extent permitted // by a licensing agreement from CORERIVER Semiconductor Co., Ltd. // // ----------------------------------------------------------------------- // *** Subject : Midas230.H (ver 0.3) // ----------------------------------------------------------------------- // Header file for the GenCore Turbo midas230 //************************************************************************** #ifndef M230_HEADER_FILE #define M230_HEADER_FILE 1 /*=========================================================================*/ /*------- Define of Byte Registers ---------------------------*/ /*=========================================================================*/ sfr P0 = 0x80; sfr SP = 0x81; sfr DPL = 0x82; sfr DPH = 0x83; sfr PCON = 0x87; sfr TCON = 0x88; sfr TMOD = 0x89; sfr TL0 = 0x8A; sfr TL1 = 0x8B; sfr TH0 = 0x8C; sfr TH1 = 0x8D; sfr P1 = 0x90; sfr EXIF = 0x91; sfr RINGCON = 0x95; sfr OSCBIAS = 0x96; sfr OSCREF = 0x97; sfr P2 = 0xA0; sfr IE = 0xA8; sfr IP = 0xB8; sfr OSCICN = 0xBE; sfr PMR = 0xC4; sfr STATUS = 0xC5; sfr LVDCFG = 0xC6; sfr PSW = 0xD0; sfr P0TYPE = 0xD4; sfr P1TYPE = 0xD5; sfr P2TYPE = 0xD6; sfr WDCON = 0xD8; sfr PWMCON = 0xDC; sfr PWMD = 0xDE; sfr ACC = 0xE0; sfr ADCSELH = 0xE1; sfr ADCSEL = 0xE2; sfr ALTSEL = 0xE3; sfr P0SEL = 0xE4; sfr P1SEL = 0xE5; sfr P2SEL = 0xE6; sfr ADCR = 0xEE; sfr ADCON = 0xEF; sfr B = 0xF0; sfr P0DIR = 0xF4; sfr P1DIR = 0xF5; sfr P2DIR = 0xF6; sfr IAPWEN = 0xFC; sfr IAPCON = 0xFD; sfr IAPDAT = 0xFE; /* ------- End of Byte Registers ----------------------------- */ /*========================================================================*/ /*------- Define of Bit Register ----------------------------*/ /*========================================================================*/ /*------------------------------------------------ P0(80h) Bit Register ------------------------------------------------*/ sbit P00 = 0x80; sbit P01 = 0x81; sbit P02 = 0x82; sbit P03 = 0x83; sbit P04 = 0x84; sbit P05 = 0x85; sbit P06 = 0x86; sbit P07 = 0x87; /*------------------------------------------------ TCON(88h) Bit Register ------------------------------------------------*/ sbit IT0 = 0x88; sbit IE0 = 0x89; sbit IT1 = 0x8A; sbit IE1 = 0x8B; sbit TR0 = 0x8C; sbit TF0 = 0x8D; sbit TR1 = 0x8E; sbit TF1 = 0x8F; /*------------------------------------------------ P1(90h) Bit Register ------------------------------------------------*/ sbit P10 = 0x90; sbit P11 = 0x91; sbit P12 = 0x92; /*------------------------------------------------ P2(A0h) Bit Register ------------------------------------------------*/ sbit P20 = 0xA0; sbit P21 = 0xA1; sbit P22 = 0xA2; sbit P23 = 0xA3; sbit P24 = 0xA4; sbit P25 = 0xA5; sbit P26 = 0xA6; /*------------------------------------------------ IE(A8h) Bit Register ------------------------------------------------*/ sbit EX0 = 0xA8; sbit ET0 = 0xA9; sbit EX1 = 0xAA; sbit ET1 = 0xAB; sbit EWDT = 0xAC; sbit EPWM = 0xAD; sbit EADC = 0xAE; sbit EA = 0xAF; /*------------------------------------------------ IP(B8h) Bit Register ------------------------------------------------*/ sbit PX0 = 0xB8; sbit PT0 = 0xB9; sbit PX1 = 0xBA; sbit PT1 = 0xBB; sbit PWDT = 0xBC; sbit PPWM = 0xBD; sbit PADC = 0xBE; /*------------------------------------------------ PSW(D0h) Bit Register ------------------------------------------------*/ sbit P = 0xD0; sbit F1 = 0xD1; sbit OV = 0xD2; sbit RS0 = 0xD3; sbit RS1 = 0xD4; sbit F0 = 0xD5; sbit AC = 0xD6; sbit CY = 0xD7; /*------------------------------------------------ WDCON(D8h) Bit Register ------------------------------------------------*/ sbit RWT = 0xD8; sbit EWT = 0xD9; sbit WTRF = 0xDA; sbit WDIF = 0xDB; sbit WDM = 0xDD; sbit WD0 = 0xDE; sbit WD1 = 0xDF; /*------------------------------------------------ ACC(E0h) Bit Register ------------------------------------------------*/ sbit ACC0 = 0xE0; sbit ACC1 = 0xE1; sbit ACC2 = 0xE2; sbit ACC3 = 0xE3; sbit ACC4 = 0xE4; sbit ACC5 = 0xE5; sbit ACC6 = 0xE6; sbit ACC7 = 0xE7; /*------------------------------------------------ B(F0h) Bit Register ------------------------------------------------*/ sbit B0 = 0xF0; sbit B1 = 0xF1; sbit B2 = 0xF2; sbit B3 = 0xF3; sbit B4 = 0xF4; sbit B5 = 0xF5; sbit B6 = 0xF6; sbit B7 = 0xF7; /* ------- End of Bit Register ---------------------------------- */ /*=========================================================================*/ /*------- Define of Bit Values --------------------------*/ /*=========================================================================*/ /*------------------------------------------------ P0 (80h) Bit Values ------------------------------------------------*/ #define P0_0_ 0x01 #define P0_1_ 0x02 #define P0_2_ 0x04 #define P0_3_ 0x08 #define P0_4_ 0x10 #define P0_5_ 0x20 #define P0_6_ 0x40 #define P0_7_ 0x80 /*------------------------------------------------ SP (81h) Bit Values ------------------------------------------------*/ #define SP0_ 0x01 #define SP1_ 0x02 #define SP2_ 0x04 #define SP3_ 0x08 #define SP4_ 0x10 #define SP5_ 0x20 #define SP6_ 0x40 #define SP7_ 0x80 /*------------------------------------------------ DPL (82h) Bit Values ------------------------------------------------*/ #define DPL0_ 0x01 #define DPL1_ 0x02 #define DPL2_ 0x04 #define DPL3_ 0x08 #define DPL4_ 0x10 #define DPL5_ 0x20 #define DPL6_ 0x40 #define DPL7_ 0x80 /*------------------------------------------------ DPH (83h) Bit Values ------------------------------------------------*/ #define DPH0_ 0x01 #define DPH1_ 0x02 #define DPH2_ 0x04 #define DPH3_ 0x08 #define DPH4_ 0x10 #define DPH5_ 0x20 #define DPH6_ 0x40 #define DPH7_ 0x80 /*------------------------------------------------ PCON (87h) Bit Values ------------------------------------------------*/ #define IDL_ 0x01 #define PD_ 0x02 #define GF0_ 0x04 #define GF1_ 0x08 #define POF_ 0x10 /*------------------------------------------------ TCON (88h)Bit Values ------------------------------------------------*/ #define IT0_ 0x01 #define IE0_ 0x02 #define IT1_ 0x04 #define IE1_ 0x08 #define TR0_ 0x10 #define TF0_ 0x20 #define TR1_ 0x40 #define TF1_ 0x80 /*------------------------------------------------ TMOD (89h) Bit Values ------------------------------------------------*/ #define M0_ 0x01 #define M1_ 0x02 #define CT_ 0x04 #define GATE_ 0x08 /*------------------------------------------------ TL0 (8Ah) Bit Values ------------------------------------------------*/ #define TL0_0_ 0x01 #define TL0_1_ 0x02 #define TL0_2_ 0x04 #define TL0_3_ 0x08 #define TL0_4_ 0x10 #define TL0_5_ 0x20 #define TL0_6_ 0x40 #define TL0_7_ 0x80 /*------------------------------------------------ TL1 (8Bh) Bit Values ------------------------------------------------*/ #define TL1_0_ 0x01 #define TL1_1_ 0x02 #define TL1_2_ 0x04 #define TL1_3_ 0x08 #define TL1_4_ 0x10 #define TL1_5_ 0x20 #define TL1_6_ 0x40 #define TL1_7_ 0x80 /*------------------------------------------------ TH0 (8Ch) Bit Values ------------------------------------------------*/ #define TH0_0_ 0x01 #define TH0_1_ 0x02 #define TH0_2_ 0x04 #define TH0_3_ 0x08 #define TH0_4_ 0x10 #define TH0_5_ 0x20 #define TH0_6_ 0x40 #define TH0_7_ 0x80 /*------------------------------------------------ TH1 (8Dh) Bit Values ------------------------------------------------*/ #define TH1_0_ 0x01 #define TH1_1_ 0x02 #define TH1_2_ 0x04 #define TH1_3_ 0x08 #define TH1_4_ 0x10 #define TH1_5_ 0x20 #define TH1_6_ 0x40 #define TH1_7_ 0x80 /*------------------------------------------------ P1 (90h) Bit Values ------------------------------------------------*/ #define P1_0_ 0x01 #define P1_1_ 0x02 #define P1_2_ 0x04 /*------------------------------------------------ EXIF (91h) Bit Values ------------------------------------------------*/ #define BGS_ 0x01 #define RGSL_ 0x02 #define RGMD_ 0x04 #define XTRG_ 0x08 /*------------------------------------------------ RINGCON (95h) Bit Values ------------------------------------------------*/ #define S0_ 0x01 #define S1_ 0x02 #define S2_ 0x04 #define S3_ 0x08 #define S4_ 0x10 #define S5_ 0x20 #define S6_ 0x40 #define S7_ 0x80 /*------------------------------------------------ OSCBIAS(96h) Bit Values ------------------------------------------------*/ #define S0_ 0x01 #define S1_ 0x02 #define S2_ 0x04 #define S3_ 0x08 #define S4_ 0x10 #define S5_ 0x20 #define S6_ 0x40 #define S7_ 0x80 /*------------------------------------------------ OSCREF(97h) Bit Values ------------------------------------------------*/ #define S0_ 0x01 #define S1_ 0x02 #define S2_ 0x04 #define S3_ 0x08 #define S4_ 0x10 /*------------------------------------------------ P2 (A0h) Bit Values ------------------------------------------------*/ #define P2_0_ 0x01 #define P2_1_ 0x02 #define P2_2_ 0x04 #define P2_3_ 0x08 #define P2_4_ 0x10 #define P2_5_ 0x20 #define P2_6_ 0x40 /*------------------------------------------------ IE (A8h) Bit Values ------------------------------------------------*/ #define EX0_ 0x01 #define ET0_ 0x02 #define EX1_ 0x04 #define ET1_ 0x08 #define EWDT_ 0x10 #define EPWM_ 0x20 #define EADC_ 0x40 #define EA_ 0x80 /*------------------------------------------------ IP (B8h) Bit Values ------------------------------------------------*/ #define PX0_ 0x01 #define PT0_ 0x02 #define PX1_ 0x04 #define PT1_ 0x08 #define PWDT_ 0x10 #define PPWM_ 0x20 #define PADC_ 0x40 /*------------------------------------------------ OSCICN (BEh) Bit Value ------------------------------------------------*/ #define DIV0_ 0x01 #define DIV1_ 0x02 #define RINGON_ 0x04 #define DIV2_ 0x08 /*------------------------------------------------ PMR (C4h)Bit Values ------------------------------------------------*/ #define XTOFF_ 0x08 /*------------------------------------------------ STATUS (C5h)Bit Values ------------------------------------------------*/ #define XTUP_ 0x10 /*------------------------------------------------ LVDCFG (C6h)Bit Values ------------------------------------------------*/ #define CFG0_ 0x01 #define CFG1_ 0x02 #define CFG2_ 0x04 #define CFG3_ 0x08 #define CFG4_ 0x10 #define PFI_ 0x20 #define EPFI_ 0x40 #define EPFR_ 0x80 /*------------------------------------------------ PSW (D0h) Bit Values ------------------------------------------------*/ #define P_ 0x01 #define F1_ 0x02 #define OV_ 0x04 #define RS0_ 0x08 #define RS1_ 0x10 #define F0_ 0x20 #define AC_ 0x40 #define CY_ 0x80 /*------------------------------------------------ P0TYPE (D4h) Bit Values ------------------------------------------------*/ #define P0TYPE_0_ 0x01 #define P0TYPE_1_ 0x02 #define P0TYPE_2_ 0x04 #define P0TYPE_3_ 0x08 #define P0TYPE_4_ 0x10 #define P0TYPE_5_ 0x20 #define P0TYPE_6_ 0x40 #define P0TYPE_7_ 0x80 /*------------------------------------------------ P1TYPE (D5h) Bit Values ------------------------------------------------*/ #define P1TYPE_0_ 0x01 #define P1TYPE_1_ 0x02 #define P1TYPE_2_ 0x04 /*------------------------------------------------ P2TYPE (D6h) Bit Values ------------------------------------------------*/ #define P2TYPE_0_ 0x01 #define P2TYPE_1_ 0x02 #define P2TYPE_2_ 0x04 #define P2TYPE_3_ 0x08 #define P2TYPE_4_ 0x10 #define P2TYPE_5_ 0x20 #define P2TYPE_6_ 0x40 /*------------------------------------------------ WDCON (D8h) Bit Values ------------------------------------------------*/ #define RWT_ 0x01 #define EWT_ 0x02 #define WTRF_ 0x04 #define WDIF_ 0x08 #define WDM_ 0x20 #define WD0_ 0x40 #define WD1_ 0x80 /*------------------------------------------------ PWMCON (DCh) Bit Value ------------------------------------------------*/ #define RUN_P0_ 0x01 #define CLR_P0_ 0x02 #define PWMF_ 0x04 #define PS0_P0_ 0x10 #define PS1_P0_ 0x20 #define PS2_P0_ 0x40 #define PWM06_ 0x80 /*------------------------------------------------ PWMD (DEh) Bit Values ------------------------------------------------*/ #define PWMD0_ 0x01 #define PWMD1_ 0x02 #define PWMD2_ 0x04 #define PWMD3_ 0x08 #define PWMD4_ 0x10 #define PWMD5_ 0x20 #define PWMD6_ 0x40 #define PWMD7_ 0x80 /*------------------------------------------------ ACC (E0h)Bit Values ------------------------------------------------*/ #define ACC0_ 0x01 #define ACC1_ 0x02 #define ACC2_ 0x04 #define ACC3_ 0x08 #define ACC4_ 0x10 #define ACC5_ 0x20 #define ACC6_ 0x40 #define ACC7_ 0x80 /*------------------------------------------------ ADCSELH (E1h) Bit Value ------------------------------------------------*/ #define ADC4B_ 0x01 #define ADC5B_ 0x02 #define ADC6B_ 0x04 #define ADC7B_ 0x08 #define ADC8B_ 0x10 #define ADC9B_ 0x20 #define ADC10B_ 0x40 #define ADC11B_ 0x80 /*------------------------------------------------ ADCSEL (E2h) Bit Value ------------------------------------------------*/ #define CH0_ 0x01 #define CH1_ 0x02 #define CH2_ 0x04 #define CH3_ 0x08 #define ADC0B_ 0x10 #define ADC1B_ 0x20 #define ADC2B_ 0x40 #define ADC3B_ 0x80 /*------------------------------------------------ ALTSEL (E3h) Bit Value ------------------------------------------------*/ #define TVO_ 0x08 #define PWM00_ 0x10 #define CLO_ 0x20 #define IORSTEN_ 0x40 #define IOXEN_ 0x80 /*------------------------------------------------ P0SEL (E4h) Bit Values ------------------------------------------------*/ #define P0SEL_0_ 0x01 #define P0SEL_1_ 0x02 #define P0SEL_2_ 0x04 #define P0SEL_3_ 0x08 #define P0SEL_4_ 0x10 #define P0SEL_5_ 0x20 #define P0SEL_6_ 0x40 #define P0SEL_7_ 0x80 /*------------------------------------------------ P1SEL (E5h) Bit Values ------------------------------------------------*/ #define P1SEL_0_ 0x01 #define P1SEL_1_ 0x02 #define P1SEL_2_ 0x04 /*------------------------------------------------ P2SEL (E6h) Bit Values ------------------------------------------------*/ #define P2SEL_0_ 0x01 #define P2SEL_1_ 0x02 #define P2SEL_2_ 0x04 #define P2SEL_3_ 0x08 #define P2SEL_4_ 0x10 #define P2SEL_5_ 0x20 #define P2SEL_6_ 0x40 /*------------------------------------------------ ADCR (EEh) Bit Values ------------------------------------------------*/ #define SAR2 0x01 #define SAR3_ 0x02 #define SAR4_ 0x04 #define SAR5_ 0x08 #define SAR6_ 0x10 #define SAR7_ 0x20 #define SAR8_ 0x40 #define SAR9_ 0x80 /*------------------------------------------------ ADCON (EFh) Bit Values ------------------------------------------------*/ #define SAR0 0x01 #define SAR1_ 0x02 #define ADIV0_ 0x04 #define ADIV1_ 0x08 #define ADCF_ 0x10 #define AD_END_ 0x20 #define AD_REQ_ 0x40 #define AD_EN_ 0x80 /*------------------------------------------------ B (F0h) Bit Values ------------------------------------------------*/ #define B0_ 0x01 #define B1_ 0x02 #define B2_ 0x04 #define B3_ 0x08 #define B4_ 0x10 #define B5_ 0x20 #define B6_ 0x40 #define B7_ 0x80 /*------------------------------------------------ P0DIR (F4h) Bit Values ------------------------------------------------*/ #define P0DIR_0_ 0x01 #define P0DIR_1_ 0x02 #define P0DIR_2_ 0x04 #define P0DIR_3_ 0x08 #define P0DIR_4_ 0x10 #define P0DIR_5_ 0x20 #define P0DIR_6_ 0x40 #define P0DIR_7_ 0x80 /*------------------------------------------------ P1DIR (F5h) Bit Values ------------------------------------------------*/ #define P1DIR_0_ 0x01 #define P1DIR_1_ 0x02 #define P1DIR_2_ 0x04 /*------------------------------------------------ P2DIR (F6h) Bit Values ------------------------------------------------*/ #define P2DIR_0_ 0x01 #define P2DIR_1_ 0x02 #define P2DIR_2_ 0x04 #define P2DIR_3_ 0x08 #define P2DIR_4_ 0x10 #define P2DIR_5_ 0x20 #define P2DIR_6_ 0x40 /*------------------------------------------------ IAPWEN (FCh) Bit Value ------------------------------------------------*/ #define WEN0_ 0x01 #define WEN1_ 0x02 #define WEN2_ 0x04 #define WEN3_ 0x08 #define WEN4_ 0x10 #define WEN5_ 0x20 #define WEN6_ 0x40 #define WEN7_ 0x80 /*------------------------------------------------ IAPCON (FDh) Bit Value ------------------------------------------------*/ #define OPS0_ 0x01 #define OPS1_ 0x02 #define RGS0_ 0x04 #define RGS1_ 0x08 /*------------------------------------------------ IAPDAT (FEh) Bit Value ------------------------------------------------*/ #define DAT0_ 0x01 #define DAT1_ 0x02 #define DAT2_ 0x04 #define DAT3_ 0x08 #define DAT4_ 0x10 #define DAT5_ 0x20 #define DAT6_ 0x40 #define DAT7_ 0x80 /* ------- End of Bit Values ---------------------------------- */ /*=========================================================================*/ /*------- Define of Interrupt Vectors & Register Banks -----------*/ /*=========================================================================*/ /*------------------------------------------------ Interrupt Vectors: Interrupt Address = (Number * 8) + 3 ------------------------------------------------*/ #define INT0B_VECTOR 0 /* 0x03 External Interrupt 0 */ #define TF0_VECTOR 1 /* 0x0B Timer 0 */ #define INT1B_VECTOR 2 /* 0x13 External Interrupt 1 */ #define TF1_VECTOR 3 /* 0x1B Timer 1 */ #define WDT_VECTOR 4 /* 0x23 WDT */ #define PWM_VECTOR 5 /* 0x2B PWM */ #define LVD_VECTOR 6 /* 0x33 LVD */ #define ADC_VECTOR 7 /* 0x3B ADC */ /*------------------------------------------------ Register Banks ------------------------------------------------*/ #define REGISTER_BANK_0 0 /* Register Bank 0 */ #define REGISTER_BANK_1 1 /* Register Bank 1 */ #define REGISTER_BANK_2 2 /* Register Bank 2 */ #define REGISTER_BANK_3 3 /* Register Bank 3 */ /*----------------------------------------------*/ /* ------- End of Interrupt Vectors & Register Banks ------------ */ #endif